NXP Semiconductors /MIMXRT1052 /CSI /CSICR3

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Interpret as CSICR3

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ECC_AUTO_EN_0)ECC_AUTO_EN 0 (ECC_INT_EN_0)ECC_INT_EN 0 (ZERO_PACK_EN_0)ZERO_PACK_EN 0 (TWO_8BIT_SENSOR_0)TWO_8BIT_SENSOR 0 (RxFF_LEVEL_0)RxFF_LEVEL 0 (HRESP_ERR_EN_0)HRESP_ERR_EN 0 (STATFF_LEVEL_0)STATFF_LEVEL 0 (DMA_REQ_EN_SFF_0)DMA_REQ_EN_SFF 0 (DMA_REQ_EN_RFF_0)DMA_REQ_EN_RFF 0 (DMA_REFLASH_SFF_0)DMA_REFLASH_SFF 0 (DMA_REFLASH_RFF_0)DMA_REFLASH_RFF 0 (FRMCNT_RST_0)FRMCNT_RST 0FRMCNT

FRMCNT_RST=FRMCNT_RST_0, DMA_REFLASH_SFF=DMA_REFLASH_SFF_0, HRESP_ERR_EN=HRESP_ERR_EN_0, DMA_REFLASH_RFF=DMA_REFLASH_RFF_0, DMA_REQ_EN_RFF=DMA_REQ_EN_RFF_0, RxFF_LEVEL=RxFF_LEVEL_0, ECC_INT_EN=ECC_INT_EN_0, ECC_AUTO_EN=ECC_AUTO_EN_0, DMA_REQ_EN_SFF=DMA_REQ_EN_SFF_0, STATFF_LEVEL=STATFF_LEVEL_0, ZERO_PACK_EN=ZERO_PACK_EN_0, TWO_8BIT_SENSOR=TWO_8BIT_SENSOR_0

Description

CSI Control Register 3

Fields

ECC_AUTO_EN

Automatic Error Correction Enable

0 (ECC_AUTO_EN_0): Auto Error correction is disabled.

1 (ECC_AUTO_EN_1): Auto Error correction is enabled.

ECC_INT_EN

Error Detection Interrupt Enable

0 (ECC_INT_EN_0): No interrupt is generated when error is detected. Only the status bit ECC_INT is set.

1 (ECC_INT_EN_1): Interrupt is generated when error is detected.

ZERO_PACK_EN

Dummy Zero Packing Enable

0 (ZERO_PACK_EN_0): Zero packing disabled

1 (ZERO_PACK_EN_1): Zero packing enabled

TWO_8BIT_SENSOR

Two 8-bit Sensor Mode

0 (TWO_8BIT_SENSOR_0): Only one sensor is connected.

1 (TWO_8BIT_SENSOR_1): Two 8-bit sensors are connected or one 16-bit sensor is connected.

RxFF_LEVEL

RxFIFO Full Level

0 (RxFF_LEVEL_0): 4 Double words

1 (RxFF_LEVEL_1): 8 Double words

2 (RxFF_LEVEL_2): 16 Double words

3 (RxFF_LEVEL_3): 24 Double words

4 (RxFF_LEVEL_4): 32 Double words

5 (RxFF_LEVEL_5): 48 Double words

6 (RxFF_LEVEL_6): 64 Double words

7 (RxFF_LEVEL_7): 96 Double words

HRESP_ERR_EN

Hresponse Error Enable. This bit enables the hresponse error interrupt.

0 (HRESP_ERR_EN_0): Disable hresponse error interrupt

1 (HRESP_ERR_EN_1): Enable hresponse error interrupt

STATFF_LEVEL

STATFIFO Full Level

0 (STATFF_LEVEL_0): 4 Double words

1 (STATFF_LEVEL_1): 8 Double words

2 (STATFF_LEVEL_2): 12 Double words

3 (STATFF_LEVEL_3): 16 Double words

4 (STATFF_LEVEL_4): 24 Double words

5 (STATFF_LEVEL_5): 32 Double words

6 (STATFF_LEVEL_6): 48 Double words

7 (STATFF_LEVEL_7): 64 Double words

DMA_REQ_EN_SFF

DMA Request Enable for STATFIFO

0 (DMA_REQ_EN_SFF_0): Disable the dma request

1 (DMA_REQ_EN_SFF_1): Enable the dma request

DMA_REQ_EN_RFF

DMA Request Enable for RxFIFO

0 (DMA_REQ_EN_RFF_0): Disable the dma request

1 (DMA_REQ_EN_RFF_1): Enable the dma request

DMA_REFLASH_SFF

Reflash DMA Controller for STATFIFO

0 (DMA_REFLASH_SFF_0): No reflashing

1 (DMA_REFLASH_SFF_1): Reflash the embedded DMA controller

DMA_REFLASH_RFF

Reflash DMA Controller for RxFIFO

0 (DMA_REFLASH_RFF_0): No reflashing

1 (DMA_REFLASH_RFF_1): Reflash the embedded DMA controller

FRMCNT_RST

Frame Count Reset. Resets the Frame Counter. (Cleared automatically after reset is done)

0 (FRMCNT_RST_0): Do not reset

1 (FRMCNT_RST_1): Reset frame counter immediately

FRMCNT

Frame Counter

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